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Principal Physical Verification Engineer (d/m/f)

ams-OSRAM AG
Unterpremstätten, ST

Direkt bewerben

Details zur Stelle

Vollzeit
vor 12 Tagen

Qualifikationen

Master
Bachelor

Vollständige Stellenbeschreibung

Sense the power of light

The ams OSRAM Group is a global leader in innovative light and sensor solutions. With more than 110 years of industry experience, we combine engineering excellence and global manufacturing with a passion for cutting-edge innovation enabling transformative advancements in the automotive, industrial, medical, and consumer industries. “Sense the power of light” – our success is based on the deep understanding of the potential of light and distinct portfolio of emitter and sensor technologies. Around 19,700 employees worldwide drive innovations alongside societal megatrends.
Find out more about us on https://ams-osram.com

Your new responsibilities

Develop and maintain Synopsys IC Validator (ICV), Siemens Calibre, Cadence PVS rule decks for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and antenna verification across multiple semiconductor technologies
Execute physical signoff verification flows using Synopsys IC Validator, Simens Calibre, Cadence PVS and analyze verification results to ensure tape-out readiness and compliance with foundry requirements
Create and optimize DFM and pattern-matching checks to improve manufacturability, yield, reliability, and process robustness
Investigate and resolve complex verification violations by performing root-cause analysis and collaborating closely with layout engineers, circuit designers, and technology teams
Develop automation and regression frameworks to improve verification efficiency, rule quality, runtime performance, and result tracking
Support technology qualification and methodology development by evaluating new process nodes, validating rule implementations, and establishing golden signoff flows
Integrate verification results into the overall signoff process, including DRC, LVS, ERC, antenna, DFM, and parasitic extraction flows, ensuring a robust and scalable verification methodology

Who we are looking for

Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or a related field
Minimum of 10 years experience in semiconductor industry
Strong understanding of semiconductor manufacturing and IC design fundamentals, including CMOS technologies, layout methodologies, parasitic effects, reliability, and signoff requirements
Hands-on experience with Physical Verification tools, especially Synopsys IC Validator (ICV), and familiarity with DRC, LVS, ERC, Antenna, and DFM verification flows
Programming and automation skills in languages such as Python, Tcl, Perl, Shell, or SKILL to develop verification utilities, regression frameworks, and automated workflows
Strong analytical skills: ability to investigate complex DRC, LVS, ERC, and DFM violations, identify root causes, and develop effective solutions
Attention to Detail: strong focus on accuracy and consistency, ensuring that even subtle rule violations or verification issues are identified before tape-out
Able to work effectively across multidisciplinary teams, supporting design, layout, technology, reliability, and manufacturing groups
Fluent English, German would be a beneficial but not a must. Ability to explain verification findings clearly to layout engineers, circuit designers, CAD teams, and foundry partners

We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). We offer a higher compensation depending on your expertise and skills.

Please contact Hana Krsul for further information via [email protected] or +43 664 9665611.

Direkt bewerben

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