19 beste Stellen als science research development in wien – aktuell auf Personalsuche

Senior Formal Verification Engineer
TechBiz Global GmbH —Wien, W
- Vollzeit
- Homeoffice
- Doktorat
- Master
- Bachelor
Direkt bewerben
Business Analytics Lead (m/f/d)
Roche —Wien, W
- Vollzeit
- Homeoffice
- Bachelor
1 Tag
AI Innovation & Solution Engineer (f/m/d)
Austrian Institute of Technology —Wien, W
- Doktorat
- Master
Software Engineer, CV
Snapchat —Wien, W
- Vollzeit
- Bachelor
Principal Investigator (f/m/d) - Translational Medicine for Pediatric Cancer
St. Anna Kinderkrebsforschung GmbH —Wien, W
- Vollzeit
- Doktorat
Principal Investigator (f/m/d) – Cellular & Immuno-Therapies
St. Anna Kinderkrebsforschung GmbH —Wien, W
- Vollzeit
- Doktorat
Tenure-Track Professorship in Security, Society and the Global East
Universität Wien —Wien, W
- Doktorat
- Master
- Bachelor
Head of Precision Oncology (f/m/d)
St. Anna Kinderkrebsforschung GmbH —Wien, W
- Vollzeit
- Doktorat
Lending Solutions Expert (f/d/m)
SAP Fioneer —Wien, W
- Vollzeit
- Master
- Bachelor
Direkt bewerben
Praktikant*in, Clinical Systems (m/w/d)
MED−EL Elektromedizinische Geräte Gesellschaft m.b.H. —Wien, W
- Vollzeit
13 Tage
Deputy Director of the CEU Library (f/m/d)
Central European University CEU —Wien, W
- Vollzeit
- Master
- Bachelor
Technical Sales Manager (all genders)
Quantum Technology Laboratories GmbH —Wien, W
- Vollzeit
Direkt bewerben
1 Tag
Head of Biobank (f/m/d)
St. Anna Kinderkrebsforschung GmbH —Wien, W
- Vollzeit
- Doktorat
Contract Negotiator - Switzerland
IQVIA —Wien, W
- Vollzeit
- Homeoffice
- Bachelor
3 Std.
Safeguards Information Analyst (Open Source)(P3)
International Atomic Energy Agency —Wien, W
- Bachelor
Head of IT Infrastructure & Scientific Computing (m/f/d)
CeMM —Wien, W
- Vollzeit
SAP IT Project Manager
Institute of Science and Technology Austria (ISTA) —Wien, W
- Vollzeit
System Engineer for Optical Ground Stations (all genders)
Quantum Technology Laboratories GmbH —Wien, W
- Vollzeit
Direkt bewerben
Contract Negotiator - Austria
IQVIA —Wien, W
- Vollzeit
- Homeoffice
- Bachelor
3 Std.

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Senior Formal Verification Engineer

TechBiz Global GmbH
Wien, W

Direkt bewerben

Details zur Stelle

Vollzeit

Qualifikationen

Doktorat
Master
Bachelor

Vollständige Stellenbeschreibung

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Direkt bewerben

Erweiterte Suche

science research development Jobs in wien

Senior Formal Verification Engineer

Business Analytics Lead (m/f/d)

AI Innovation & Solution Engineer (f/m/d)

Software Engineer, CV

Principal Investigator (f/m/d) - Translational Medicine for Pediatric Cancer

Principal Investigator (f/m/d) – Cellular & Immuno-Therapies

Tenure-Track Professorship in Security, Society and the Global East

Head of Precision Oncology (f/m/d)

Lending Solutions Expert (f/d/m)

Praktikant*in, Clinical Systems (m/w/d)

Deputy Director of the CEU Library (f/m/d)

Technical Sales Manager (all genders)

Head of Biobank (f/m/d)

Contract Negotiator - Switzerland

Safeguards Information Analyst (Open Source)(P3)

Head of IT Infrastructure & Scientific Computing (m/f/d)

SAP IT Project Manager

System Engineer for Optical Ground Stations (all genders)

Contract Negotiator - Austria

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