11 beste Stellen als platform software engineer in wien – aktuell auf Personalsuche

Senior Formal Verification Engineer - Vector Unit
TechBiz Global GmbH —Wien, W
- Vollzeit
- Homeoffice
- Doktorat
- Master
- Bachelor
Direkt bewerben
1 Tag
Product Owner and DevOps Engineer (w/m/d)
Hitachi —Wien, W
- Vollzeit
- Homeoffice
13 Std.
New Logo Account Executive - Greek speaking
ServiceNow —Wien, W
- Vollzeit
Direkt bewerben
Senior Solution Sales Executive (Risk/Security)
ServiceNow —Wien, W
- Vollzeit
Direkt bewerben
Senior Mobile App Developer (m/f/d)
wikifolio Financial Technologies AG —Wien, W
- Vollzeit
Commercial Account Executive, CEE
ServiceNow —Wien, W
- Vollzeit
Direkt bewerben
Customer Success Executive - German Speaking
ServiceNow —Wien, W
- Vollzeit
Direkt bewerben
Senior Fullstack Engineer (m/w/d), Wien
TOWA GmbH —Wien, W
- Vollzeit
Direkt bewerben
14 Tage
Junior Python Engineer (f/m/d)
Adverity —Wien, W
- Vollzeit
- Homeoffice
2 Std.
Software Engineer for Dependable Systems (f/m/d)
Hitachi —Wien, W
- Vollzeit
- Homeoffice
13 Std.
Embedded Systems Engineer for Base Systems (f/m/d)
Hitachi —Wien, W
- Vollzeit
- Homeoffice
13 Std.

More jobs to discover

Find similar jobs that you might be interested in.

Senior Test Automation Engineer (m/w/d) – Gefahrenmanagementsysteme
PKE Software Solutions GmbH —Wien, W
Die PKE Software Solutions GmbH ist Teil der international tätigen PKE Gruppe und bietet flexible und skalierbare Softwarelösungen, die moderne Technologien wie…

Ich möchte aktuelle Job-E-Mails für Stellen als platform software engineer in wien erhalten

Wenn Sie sich bei Ihrem Konto anmelden, stimmen Sie den Nutzungsbedingungen, den Richtlinien zur Verwendung von Cookies sowie der Datenschutzerklärung von SimplyHired zu.

Weitere Job-Standorte erkunden

platform software engineer jobs near wien

Senior Formal Verification Engineer - Vector Unit

TechBiz Global GmbH
Wien, W

Direkt bewerben

Details zur Stelle

Vollzeit
vor 1 Tag

Qualifikationen

Doktorat
Master
Bachelor

Vollständige Stellenbeschreibung

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Must Have

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Essential Soft Skills

An adversarial, gap-seeking mindset — instinctively asks "who actually checks this?" — with a strong umbrella view of the whole core.
Clear communication across DV, design, and software teams; writes verification plans others can follow.

Direkt bewerben

Erweiterte Suche

platform software engineer Jobs in wien

Senior Formal Verification Engineer - Vector Unit

Product Owner and DevOps Engineer (w/m/d)

New Logo Account Executive - Greek speaking

Senior Solution Sales Executive (Risk/Security)

Senior Mobile App Developer (m/f/d)

Commercial Account Executive, CEE

Customer Success Executive - German Speaking

Senior Fullstack Engineer (m/w/d), Wien

Junior Python Engineer (f/m/d)

Software Engineer for Dependable Systems (f/m/d)

Embedded Systems Engineer for Base Systems (f/m/d)

More jobs to discover

Ich möchte aktuelle Job-E-Mails für Stellen als platform software engineer in wien erhalten

Related Searches

Weitere Job-Standorte erkunden

Tools für Jobsuchende

Arbeitgebertools

Durchsuchen

Bleiben Sie in Kontakt