19 beste Stellen als engineer (python) in schwechat nö – aktuell auf Personalsuche

Senior Formal Verification Engineer - Vector Unit
TechBiz Global GmbH —Wien, W
- Vollzeit
- Homeoffice
- Doktorat
- Master
- Bachelor
Direkt bewerben
2 Std.
Software Engineer, Data Infrastructure & Acquisition - Vienna, Austria
Speechify —Wien, W
- Homeoffice
- Doktorat
- Master
- Bachelor
15 Std.
(Senior) Data Engineer (Databricks/Snowflake) (m/w/d)
Capgemini —Wien, W
Senior System Engineer (w/m/x)
BEKO Solutions GmbH —Wien, W
- Vollzeit
AI Architect (w/m/x)
Avanade —Wien, W
- Master
Senior Spezialist:in CBM & IoT für Schienenfahrzeuge
ÖBB Konzern —Wien, W
Databricks AI / ML Engineer (m/w/d)
Qualysoft —Wien, W
- Master
Direkt bewerben
IT System Engineer (w/m/d) Network-Security
Bechtle —Wien, W
Data Engineering Consultant (w/m/x) - Austria
Avanade —Wien, W
Platform Engineer (AI / Data Platform)
Qualysoft —Wien, W
Direkt bewerben
PEGA-Lead System Engineer (f/m/d)
Qualysoft —Wien, W
Direkt bewerben
Data Engineer (m/w/x)
Styria Media Group AG —Wien, W
- Vollzeit
Senior Data Engineer (m/w/x)
ÖBB Konzern —Wien, W
Network Security Engineer (m/w/d)
Anexia Holding GmbH —Wien, W
- Vollzeit
Senior System Engineer (m/w/d) – Storage & Backup
Anexia Holding GmbH —Wien, W
- Vollzeit
6 Tage
System Engineer (M/W/D)
FREQUENTIS COMSOFT GmbH —Wien, W
DATA ENGINEER (M/W/D)
CubeServ —Wien, W
Data & Analytics - Data Engineering Lead (all genders)
VIENNA INSURANCE GROUP AG Wiener Versicherung Gruppe —Wien, W
- Vollzeit
UC DevOps Engineer (m/w/d)
World-Direct eBusiness solutions GmbH —Wien, W
- Vollzeit
Direkt bewerben

More jobs to discover

Find similar jobs that you might be interested in.

Software Engineer, Data Infrastructure & Acquisition - Vienna, Austria
Speechify —Wien, W
5+ years of industry experience in software development. Experience with web crawlers, large-scale data processing workflows is a plus.
15 Std.
Associate - AI Tech Consulting (all genders) - BCG Platinion Vienna, Austria
Boston Consulting Group —Wien, W
You gained first practical experience in the IT consulting, e.g., via internships or student jobs. You'll design and optimize unique IT architectures within the…
4 Tage

Ich möchte aktuelle Job-E-Mails für Stellen als engineer (python) in schwechat nö erhalten

Wenn Sie sich bei Ihrem Konto anmelden, stimmen Sie den Nutzungsbedingungen, den Richtlinien zur Verwendung von Cookies sowie der Datenschutzerklärung von SimplyHired zu.

Weitere Job-Standorte erkunden

engineer (python) jobs near schwechat nö

Senior Formal Verification Engineer - Vector Unit

TechBiz Global GmbH
Wien, W

Direkt bewerben

Details zur Stelle

Vollzeit
vor 2 Stunden

Qualifikationen

Doktorat
Master
Bachelor

Vollständige Stellenbeschreibung

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Must Have

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Essential Soft Skills

An adversarial, gap-seeking mindset — instinctively asks "who actually checks this?" — with a strong umbrella view of the whole core.
Clear communication across DV, design, and software teams; writes verification plans others can follow.

Direkt bewerben

Erweiterte Suche

engineer (python) Jobs in schwechat nö

Senior Formal Verification Engineer - Vector Unit

Software Engineer, Data Infrastructure & Acquisition - Vienna, Austria

(Senior) Data Engineer (Databricks/Snowflake) (m/w/d)

Senior System Engineer (w/m/x)

AI Architect (w/m/x)

Senior Spezialist:in CBM & IoT für Schienenfahrzeuge

Databricks AI / ML Engineer (m/w/d)

IT System Engineer (w/m/d) Network-Security

Data Engineering Consultant (w/m/x) - Austria

Platform Engineer (AI / Data Platform)

PEGA-Lead System Engineer (f/m/d)

Data Engineer (m/w/x)

Senior Data Engineer (m/w/x)

Network Security Engineer (m/w/d)

Senior System Engineer (m/w/d) – Storage & Backup

System Engineer (M/W/D)

DATA ENGINEER (M/W/D)

Data & Analytics - Data Engineering Lead (all genders)

UC DevOps Engineer (m/w/d)

More jobs to discover

Ich möchte aktuelle Job-E-Mails für Stellen als engineer (python) in schwechat nö erhalten

Related Searches

Weitere Job-Standorte erkunden

Tools für Jobsuchende

Arbeitgebertools

Durchsuchen

Bleiben Sie in Kontakt